Many different types and styles of memory exist to store data for computers and similar type systems. For example, random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), read only memory (ROM), programmable read only memory (PROM), electrically programmable read only memory (E-PROM), electrically erasable programmable read only memory (EEPROM) and flash memory are all presently available to accommodate data storage.
Each type of memory has its own particular advantages and disadvantages. For example, DRAM and SRAM allow individual-bits of data to be erased one at a time, but such memory loses its data when power is removed. EEPROM can alternatively be easily erased without extra exterior equipment, but has reduced data storage density, lower speed, and higher cost. EPROM, in contrast, is less expensive and has greater density but lacks ease of erasability.
Flash memory, has become a popular type of memory because it combines the advantages of the high density and low cost of EPROM with the electrical erasability of EEPROM. Flash memory can be rewritten and can hold its contents without power, and thus is nonvolatile. It is used in many portable electronic products, such as cell phones, portable computers, voice recorders, etc. as well as in many larger electronic systems, such as cars, planes, industrial control systems, etc.
Flash memory is generally constructed of many memory cells where, generally, single bits of data are stored in and read from respective memory cells. The cells are generally programmed by hot electron injection and erased by Fowler-Nordheim tunneling or other mechanisms. As with many aspects of the semiconductor industry, there is a continuing desire and effort to achieve higher device packing densities and increase the number of memory cells on a semiconductor wafer. Similarly, increased device speed and performance are also desired to allow more data to be stored on smaller memory devices.
Individual flash memory cells are organized into individually addressable units or groups, which are accessed for read, program, or erase operations through address decoding circuitry. The individual memory cells are typically comprised of a semiconductor structure adapted for storing a bit of data and includes appropriate decoding and group selection circuitry, as well as circuitry to provide voltages to the cells being operated upon.
As with many aspects of the semiconductor industry, there is a continuing desire to scale down device dimensions to achieve higher device packing densities on semiconductor wafers. Similarly, increased device speed and performance are also desired to allow more data to be, stored on smaller memory devices. Accordingly, there are ongoing efforts to, among other things, increase the number of memory cells that can be packed on a semiconductor wafer (or die).
For example, another type of flash memory is dual element nitride storage flash memory, which allows multiple bits to be stored in a single cell. In this technology, a memory cell is essentially split into two identical (mirrored) or complementary regions, each of which is formulated for storing one of two independent bits or elements. Each dual element nitride storage flash memory cell, like a traditional cell, has a gate, a source, and a drain. However, unlike a traditional stacked gate cell in which the source is always connected to an electrical source and the drain is always connected to an electrical drain, respective dual element nitride storage flash memory cells can have the connections of the source and drain reversed during operation to permit the storing of two bits or elements.
In the continued effort to scale down device dimensions and to achieve higher device packing densities, increasingly large memory arrays or groupings are sought-out. Such increased memory groupings may put additional accessing and control duties on the processor or central processing unit (CPU) utilizing these large memory groupings, particularly where the more complex multi-level and multi-bit memory arrays are used. In addition, ever increasing numbers of peripheral devices also demand attention of the processor to which they are attached. One way that these demands can be off-loaded from the CPU is by utilizing a serial peripheral interface (SPI) to take over such memory access/control and peripheral interfacing duties.
However, as such peripheral needs and memory sizes continue to grow, the addressing requirements of current SPI devices will also tend to grow beyond the current 3-byte addressing scheme which limits memory addressing capability to 128 Mb. In addition, the 3-byte addressing is often hard-coded in the processors of current SPI-processor based chip-sets. Although new SPI-processor chip-sets could be designed that overcome these 3-byte addressing limitations, such system redesigns could be costly and time consuming and may not allow the use of current and legacy devices.
In view of the foregoing, a continued need exists for an improved SPI system and method of addressing larger arrays of flash memory cells using current and legacy devices that allow backward compatibility without costly and time consuming redesign.